Split gate memory cells have found a particular use in non-volatile memories (NVMs) that have many applications and the applications are continuing for the foreseeable future. The methods for program and erase have been the subject of continuous study with a view to achieving desired or improved program and erase times with the lower voltages being used. Program and erase must still provide a sufficient differential between states for reading. Generally the bigger the difference the more effective and reliable is the reading of the state. Issues such as read disturb also continue to be concerns and must be taken into account in any design. Further there is the continuing improvement in lithography and processes so that dimensions continue to reduce, and the NVM cells should be designed to take advantage of the reduced dimensions. A variety of different techniques have been developed to address these issues, but there is a continuing desire for further improvement.
Thus, there is a need for a technique for improving on one or more of the issues described above.